Today, a trend of high-density NMOS NVSRAM memory more than 8 Mb is required. Therefore, besides the fixed six transistors (6T) of each SRAM cell, the number of transistors of each NMOS Flash cell should be minimized as much as possible.
Traditionally, a 12T NVSRAM cell comprises one 6T LV SRAM cell and one 6T HV Flash cell including paired 3T Flash strings. Each SRAM cell has paired storage nodes of Q and QB connected to two inputs of the paired Flash strings. Each 3T Flash string further includes one (high-voltage) HV Select transistor located on top and another one on bottom, with one 2-poly HV flash transistor sandwiched in the middle of above two HV Select transistors.
Each paired drain nodes of the paired Flash strings are preferably connected to each paired nodes of Q and QB of each 6T LV SRAM cell directly. Conversely, the paired source nodes of each paired Flash strings are connected to a common VDD power supply to provide the different current flows to charge each paired nodes of Q and QB at two different voltage levels for each SRAM cell's subsequent amplification through two different programmed channel threshold levels Vts of each paired Flash transistors during the Recall operation.
Although several NVSRAM approaches were disclosed before, the 12T NVSRAM using low-current FN-channel program and FN SBPI method is prevailing in the market place. The flash type can be either made of 1-poly charge-trapping SONOS or MONOS type from Cypress or 2-poly floating-gate NMOS or PMOS type from Aplus Flash Technology, Inc., or a trigate flash technology from Simtek. By 2012, the highest density of a 12T NMOS NVSRAM memory in production is 16 Mb.
There are five key fundamental operations associated with the 12T NVSRAM cell memory, as summarized here: 1) SRAM's LV Read and Write operation; 2) Flash's HV FN-channel Program operation; 3) Flash's HV FN-channel Erase operation; 4) NVSRAM Store operation; and 5) NVSRAM Recall operation.
The Store operation is defined to program each SRAM cell logic data into each corresponding Flash cell. This is like a Flash FN-channel Program operation as described in operation 2). This operation can be further divided into three sub-operations as shown below:                a) Auto-Store operation: This operation is defined to be performed when a first regular VDD power supply is removed and replaced by a second VDD back-up power supply by using an off-chip Vcap or Vbat.        b) Software-Store operation: This operation is defined to be performed during stable VDD period and is called by a defined sequence of software steps.        c) Hardware-Store operation: This operation is defined to be performed during stable VDD period and is called by a hardware pin by system Multipoint Control Unit (MCU).        
The Recall operation is defined to transfer each Flash cell logic data into each corresponding SRAM cell. This operation is like a Flash Read operation. This operation can be divided into three sub-operations as shown below:                a) Auto-Recall operation: This operation is defined to be automatically performed during the power-up period of a first regular VDD power supply once the VDD ramping voltage level reaches above the predetermined voltage, such as 80% of the final stable VDD power.        b) Software-Recall operation: This operation is defined to be performed during stable VDD period and is called by a defined sequence of software steps.        c) Hardware-Recall operation: This operation is defined to be performed during stable VDD period and is called by a hardware pin by system MCU.        
For example, in a U.S. Pat. No. 5,065,362, a 12T non-volatile RAM cell was provided with the flash cell being a 1-poly trigate cell structure. The biased conditions for program operation is: Flash word line FWL=+15V, source line FSL=0V, with Flash cell Vt≧+2V; for erase operation: FWL=−15V, FSL=0V, with Flash cell Vt≦−2V. In another example of U.S. Pat. No. 7,760,540, a 12T non-volatile SRAM cell was provided with the flash cell being a 1-poly charge-trapping SONOS or MONOS cell structure. The associated bias conditions for program operation is: FWL=+10V, FSL=0V, with Flash cell Vt≧+2V; for erase operation: FWL=−10V, FSL=0V, with Flash cell Vt≦−2V. In yet another example, as shown in a U.S. Pat. No. 7,164,608, granted to the same inventor of the present application, another 12T NVSRAM cell with a 2-poly floating-gate flash cell structure is provided. The biased conditions for program operation is: Flash word line FWL=+15V, source line FSL=0V, with Flash cell Vt≧+2V; for erase operation: FWL=−15V, FSL=0V, with Flash cell Vt≦−2V.
One big drawback of this 12T NMOS NVSRAM memory is its large 12T cell size that comprises one 6T LV SRAM cell and one 6T HV Flash cell. And each 6T Flash cell further comprises one paired 3T FStrings and each FString further comprises one top HV Select transistor, one bottom HV Select transistor, and one flash transistor sandwiched by two Select transistors in the middle.
Due to three transistors of each Flash string have to be made of all HV devices to sustain a HV of 5-7V generated by a SBPI (Self-Boosting Program-Inhibit) scheme during the FN-Channel Program operation of NVSRAM cell, the channel length of these two HV Select transistors are made relatively bigger than the ones of a LV SRAM two PMOS transistors and four NMOS transistors. As a result, it is desirable to achieve any saving of each HV Select transistor in each Flash string so as to drastically reduce the NVSRAM cell size for cost reduction.